Improved memory usage efficiency when running large programs.
Supports the new CTI 2500 Series processors, which can now be selected from the list of supported PLC types.
Maintains own network listing to allow WorkShop to enter into network mode directly when connecting.
Power flow in timer-based instructions no longer constantly toggles outputs on and off when 505 Simulator is run on faster computers.
Address ranges referenced by the MOVE instruction are now verified for proper configuration before execution.
Source and destination table pointers referenced by the Move Word with Index (MWI) instruction are now verified for proper configuration before execution.
Timer instructions now function properly when called from a cyclic RLL task.
Process variable square root values are now correctly calculated.
Up Counter (CTR) instructions, Discrete Control Alarm Timer (DCAT) instructions, Motor Control Alarm Timer (MCAT) instructions, Move Word from Table (MWFT) instructions, and Move Word to Table (MWTT) instructions are no longer affected by instruction numbers greater than 255.
Divide (DIV) instructions no longer write a result if an overflow is detected.
Word Shift Register (SHRW) instructions no longer cause word address parameters to shift one extra word in the shift register.
Instructions now always execute when they have power flow and will not execute when they do not have power flow.
Bit Pick (BITP) and Bit Clear (BITC) instructions no longer execute without power flow.
Using Startup Restore no longer results in an error during startup if shut down occurs after the execution of the final batch of an I/O Simulator recipe.
Compare (CMP) instructions now perform signed comparisons of their values.
Discrete Control Alarm Timer (DCAT) instructions no longer advance erratically.
All instructions can now read from K (Constant) memory normally.
Read-only addresses can no longer be written to when using the 505 internal addressing format.
Move Image Register to Table (MIRTT) instructions now execute properly at a length of 256.
Move Word with Index (MWI) instructions no longer pass power when encountering error situations.
Scan Matrix Compare (SMC) instructions now reset their address pointers when power flow to the instruction is disabled.
Exceeding the maximum subroutine nesting level (32) no longer results in an unexpected termination of the program.
WorkShop no longer has a problem searching for discrete addresses through Special Function Subroutine (SFSUB) instructions in ladder.
Motor Control Alarm Timer (MCAT) instructions now properly clear open and close alarm bits when the general alarm condition is no longer present.
Attempting to use a discrete address in an error status address location now properly results in an error.
Expressions processed under error conditions now produce results similar to a 505 PLC.
In IMATH expressions, the NOT operator now determines the one’s complement when used in conjunction with an integer and generates a Boolean result when used in conjunction with a discrete.
FRAC expression functions now produce proper results when used on negative numbers.
Call subroutine (CALL) instructions now allow the correct number of subroutines to be nested in a Special Function execution sequence.
Respective status bits for Fall Through Shift Register (FTSR) instructions are now cleared when the register is no longer either full or empty.
Special Function Subroutine (SFSUB) instructions are now compiled using real expressions.
PID loops now utilize loop and alarm acknowledge flags and update loop and alarm status flags appropriately.
PID loops now set bit 6 (hold in progress) of the RAMP/SOAK flag address when RAMP/SOAK is set to Hold mode.
Executing PID loops using the Deadband error mode no longer results in an invalid error value.
PID loops using a reverse acting loop now have improved error calculation.
PID loops now execute a new Special Function program if the C-Flags are modified directly from an operator interface.
Compiling Special Function programs that contain PACK Loop/Alarm instructions with a certain number of data elements no longer results in an error.
Non-loop output addresses used as remote setpoints no longer prevent loops from transitioning into Cascade mode.
Attempting to set a breakpoint on an address that is being modified by the I/O Simulator no longer results in error.
Up/Down Counter instructions now count up to the current preset (TCP) value rather than the value at the time the simulator entered Run mode.