Author: Ethan Wilke

Solutions

• The Lead-Lag instructions are executed correctly when called from Analog Alarms.
• The Read Slave Diagnostic (RSD) instruction transfers the complete slave’s diagnostic buffer to user memory.
• The Fall Through Shift Register (FTSR) instruction supports bit-of-word addresses as Status Bits.
• The Move Image Register From Table (MIRFT) instruction is supported within Master Control Relay (MCR) and Jump (JMP) ladder logic zones.

Solutions

• The correct output states of Compare instructions are retained when the instruction is within jumped networks
• Image register values of Move Word to Image Registers instructions are unchanged when the instruction is within jumped networks
• Drum instructions allow time base 0.0 in the SEC/CNT parameter
• Bit-of-Words for addresses greater than 1024 (for example, V1025, K1025, WX1025) are supported in Special Function Programs and Subroutines
• Special Function Math instructions support calculations that use long integers
• Lead-Lag instructions are correctly executed from Special Function Subroutines that are called from Loops, Alarms, or cyclic Special Function Programs
• The IN parameter of the Search Table for Not Equal instruction accepts all valid address types

Solutions

• Bit-of-word addresses that exist in SFSUB instructions in the Simulator now properly appear in search results in WorkShop.

Features

• Simulator now supports the following Special Function instructions when simulating the CTI 2500 Series controller:
  • FOR / NEXT
  • WHILE / ENDWHILE
  • SWITCH / BREAK / CASE / DEFAULT / ENDSWITCH
• Simulator now supports up to 10 parameters for the SFSUB ladder instruction when simulating the CTI 2500 Series controller.
• Bit-of-word access is now available for Special Function instructions that support expressions, element indexing, or discrete parameters when simulating CTI 2500 Series controllers.
• Special Function temporary memory size has been increased to 64 when simulating CTI 2500 Series controllers.

Solutions

• Using the PACK instruction to pack less than 16 bits into a word now properly sets the unused bits to zero when simulating CTI 2500 Series controllers.
• Lead-Lag instruction results are now consistent across controller types.
• Users may now add a password to the PLC under FasTrak Security when using the Simulator.

Solutions

• The CDB instruction now correctly checks the value of the address.
• The PID Loop Ramp/Soak Profile now properly restarts operation when the Loop Ramp/Soak number is manually reset to 0.
• The CTR instruction’s output no longer turns off when the count no longer matches the preset.
• MOD instructions are now properly evaluated within IF statements in a Special Function program.
• NOT instructions now operate correctly in parallel branches when passing power flow.
• B-memory parameters are now properly allowed in CMP instructions.
• Nested MCR instructions now operate correctly.
• Attempting to set an LTI variable to zero in the Data Window now properly displays an error.
• B-memory is now properly supported in the MIRW instruction.
• Special Function clamping for PID Loops and Analog Alarms is now consistent between 505 and CTI 2500 PLC types.
• Attempting to execute a network containing more than 16 parallel branches no longer results in an error.
• Analog Alarms are now set and reset correctly when the alarm deadband overlaps low/high alarm points.
• One-shot contacts no longer automatically execute after an online edit is made.
• Multiple instructions that use B and W addresses now execute properly.
• Special Function programs are no longer triggered when the input conditions are false.
• Cyclic Special Function programs now properly stop executing after changing to inline while online with the controller.
• Cyclic Special Function programs now properly stop executing when ‘Continue on Error’=NO.
• Address breakpoints are now properly being triggered by coil instructions.
• The PACK statement now executes properly when moving Loop and Alarm CF variables to and from Bit memory.

Solutions

• Attempting to write a Loop or Alarm containing a word address that is within five locations of the maximum configured value of the address type no longer results in an error.
• The PRINT statement will no longer prevent users from enabling their Special Function Programs and Subroutines.
• Analog Alarms now write the correct number of bits to the V-flag address when the location is discrete.
• MATH expressions no longer set an error when an address is assigned at its maximum bounds.
• The PACKRS instruction now correctly allows constants for Loop Number, Number of Steps, and Starting Step parameters.
• Instructions that require preset values to be set are now correctly set on a transition to Run Mode.
• The Find Opcode function now properly finds instruction numbers greater than 255.
• The IMC instruction now indexes its pointer value correctly during execution.
• Implied addresses are now located correctly during a Find Parameter operation.
• The DCMP, DSET, MDRUMD, MDRUMW, MWFT, MWTT, and SHRB instructions are now checked correctly for syntax errors.
• 32-bit integers are now processed correctly in Special Function instructions.
• Parameterized Bit memory may now be used as the register address in MWIR and MIRW instructions.
• The LEAD/LAG instruction now produces the correct output.
• RLL instructions with parameterized bit and word address maximum boundaries of 20 are now able to use the maximum value within their programs.
• The total number of Loops, Alarms, and Special Function Programs and Subroutines is now determined at startup based on the PLC model and is used correctly to perform syntax checks.
• DCAT, MCAT, Bit of Word Coil, Set Coil, and Reset Coil instructions now properly disable or clear their outputs when the MCR or JMP flags are turned off or on.
• The Special Function Modulo operator now reports the correct result when using real numbers where the denominator is less than 1.
• Timer-based instructions will now work properly when used in RLL subroutines.
• Analog Alarms and PID Loops are now properly clearing their low and low-low alarm flags when the process variable jumps immediately from the low end to the high or high-high alarm range.
• The integer format may now be used when using constants within conditional breakpoints.
• The SFSUB instruction now correctly ceases execution when a parameter sets the SFEC variables and the Continue on Error flag is set to No.
• The setpoint for Loops and Alarms is now being clamped properly when the remote setpoint is not in use.
• The deadband for Loops and Alarms now functions correctly when the process variable becomes negative.
• SCALE statements now properly round integer results.
• MOVE Word operations now correctly copy the last word of a parameterized word memory address (PSWA).
• PID Loops now correctly prioritize to execute in the right order.
• All Special Function programs and subroutines will now queue to execute if they have power flow enabled for at least one scan.
• Searching for inline Special Function Subroutines while online now works properly.
• The IMATH statement now produces the correct result when calculating a shift left or shift right operation into a long integer.
• The PACK TO statement now accepts a constant value as the Data Start Address.
• Entering an Alarm V-flag above Y9=8182 no longer results in an error.

Solutions

• Attempting to enable a Special Function containing SCALE or UNSCALE instructions that use indexed expressions as input parameters no longer results in an error.
• Non-fatal errors encountered in Special Functions that contain a Store operation are now correctly reported.
• Status Word STW1 is now correctly updated during RLL task execution.
• Discrete encodings that were converted from APT programs are now correctly recognized as data start addresses by the PACK instruction.
• Loop and alarm addresses that are not flagged as real numbers may now be read as integers and converted to real number addresses.
• Attempting to run a TASK instruction within an RLL subroutine will now correctly generate a syntax error.
• The PACK instruction now correctly allows discrete addresses to be used as the table address in a Pack From configuration.
• Cyclic Special Function programs containing RETURN instructions now execute properly after their first iteration.
• The PACK instruction no longer allows Status Word addresses to be used as the table address in a Pack From configuration.
• The PACK instruction now correctly allows T memory to be used as the table address in a Pack To configuration.
• The PACK instruction has been rewritten to more correctly simulate PLC behavior when using a discrete table address.
• RLL error addresses are now properly reported from the ladder syntax check.
• Power flow for branched multiple-input box instructions is now reported correctly.
• The Special Function CALL instruction now correctly passes discrete parameters.
• Parameter address types are now correctly allowed as Register Start addresses in Shift Register Status instructions when used with a table of constant length.
• Parameters specified as integer values in Pack Loop and Pack Alarm instructions are no longer being packed as real numbers.

Solutions

• Entering Run mode in certain types of user programs no longer causes an unexpected error.
• Enabling a Special Function program that contains a K-memory address indexed in an expression no longer results in a compilation error.
• Discrete parameters that are passed in SFSUB instructions in ladder are now properly checked that they are within a valid range before being compiled.
• The Error Status Address for Special Function programs is now properly checked that it is within a valid range when the program is enabled.
• The Ramp/Soak Status Bit address is now properly verified upon download of Ramp/Soak information.
• The Special Function Error Code is now updated correctly during inline SFSUB executions, and the STORE instruction now properly reports errors so that values are written in the correct order to the Error Status address.
• Write Loop and Write Alarm address values are now properly checked that they are within a valid range before they are written.
• Simulator now correctly processes discrete addresses used in loops and alarms that were originally loaded from an APT program and then saved in WorkShop.

Features

• Ladder, Special Function, and Expression compilers have been updated to find a broader range of syntax errors within a program.

Solutions

• The STW1.11 bit is now properly set and cleared during error situations.
• The PRINT instruction now decodes text instructions that are not on a word-aligned boundary.
• MOVE instructions now execute properly at a length of 256 and greater.
• PID Loops now transition properly from automatic to cascade and back.
• Attempting to launch 505 Simulator from within a copy of WorkShop that was originally installed by another user no longer results in an error.
• Attempting to upgrade the site license of a copy of 505 Simulator that was originally installed by another user no longer results in an error.
• Attempting to load a program that contains logic in an invalid location no longer causes 505 Simulator to close unexpectedly.
• Open and close alarms that occupy the same address are now properly set by the DCAT instruction.
• The value of the square root of a process variable calculation is no longer rounded before being scaled.
• Timer (TMR) instruction output nodes now stay on if the input node turns off after the timer expires.
• Valid information is now returned when reading or writing Loop Mode and Loop Status TT types.
• Error bits are now properly set after the occurrence of a non-fatal error.
• The Special Function Subroutine (SFSUB) instruction now properly sets and clears status and error bits during execution.
• Go To Subroutine (GTS, PGTS, and PGTSZ) instructions now correctly set all error bits and words when a subroutine stack overflow occurs.
• Deleting a Cyclic Special Function program that is being executed no longer causes 505 Simulator to close unexpectedly.

Features

• Improved memory usage efficiency when running large programs.
• Supports the new CTI 2500 Series processors, which can now be selected from the list of supported PLC types.
• Maintains own network listing to allow WorkShop to enter into network mode directly when connecting.

Solutions

• Power flow in timer-based instructions no longer constantly toggles outputs on and off when 505 Simulator is run on faster computers.
• Address ranges referenced by the MOVE instruction are now verified for proper configuration before execution.
• Source and destination table pointers referenced by the Move Word with Index (MWI) instruction are now verified for proper configuration before execution.
• Timer instructions now function properly when called from a cyclic RLL task.
• Process variable square root values are now correctly calculated.
• Up Counter (CTR) instructions, Discrete Control Alarm Timer (DCAT) instructions, Motor Control Alarm Timer (MCAT) instructions, Move Word from Table (MWFT) instructions, and Move Word to Table (MWTT) instructions are no longer affected by instruction numbers greater than 255.
• Divide (DIV) instructions no longer write a result if an overflow is detected.
• Word Shift Register (SHRW) instructions no longer cause word address parameters to shift one extra word in the shift register.
• Instructions now always execute when they have power flow and will not execute when they do not have power flow.
• Bit Pick (BITP) and Bit Clear (BITC) instructions no longer execute without power flow.
• Using Startup Restore no longer results in an error during startup if shut down occurs after the execution of the final batch of an I/O Simulator recipe.
• Compare (CMP) instructions now perform signed comparisons of their values.
• Discrete Control Alarm Timer (DCAT) instructions no longer advance erratically.
• All instructions can now read from K (Constant) memory normally.
• Read-only addresses can no longer be written to when using the 505 internal addressing format.
• Move Image Register to Table (MIRTT) instructions now execute properly at a length of 256.
• Move Word with Index (MWI) instructions no longer pass power when encountering error situations.
• Scan Matrix Compare (SMC) instructions now reset their address pointers when power flow to the instruction is disabled.
• Exceeding the maximum subroutine nesting level (32) no longer results in an unexpected termination of the program.
• WorkShop no longer has a problem searching for discrete addresses through Special Function Subroutine (SFSUB) instructions in ladder.
• Motor Control Alarm Timer (MCAT) instructions now properly clear open and close alarm bits when the general alarm condition is no longer present.
• Attempting to use a discrete address in an error status address location now properly results in an error.
• Expressions processed under error conditions now produce results similar to a 505 PLC.
• In IMATH expressions, the NOT operator now determines the one’s complement when used in conjunction with an integer and generates a Boolean result when used in conjunction with a discrete.
• FRAC expression functions now produce proper results when used on negative numbers.
• Call subroutine (CALL) instructions now allow the correct number of subroutines to be nested in a Special Function execution sequence.
• Respective status bits for Fall Through Shift Register (FTSR) instructions are now cleared when the register is no longer either full or empty.
• Special Function Subroutine (SFSUB) instructions are now compiled using real expressions.
• PID loops now utilize loop and alarm acknowledge flags and update loop and alarm status flags appropriately.
• PID loops now set bit 6 (hold in progress) of the RAMP/SOAK flag address when RAMP/SOAK is set to Hold mode.
• Executing PID loops using the Deadband error mode no longer results in an invalid error value.
• PID loops using a reverse acting loop now have improved error calculation.
• PID loops now execute a new Special Function program if the C-Flags are modified directly from an operator interface.
• Compiling Special Function programs that contain PACK Loop/Alarm instructions with a certain number of data elements no longer results in an error.
• Non-loop output addresses used as remote setpoints no longer prevent loops from transitioning into Cascade mode.
• Attempting to set a breakpoint on an address that is being modified by the I/O Simulator no longer results in error.
• Up/Down Counter instructions now count up to the current preset (TCP) value rather than the value at the time the simulator entered Run mode.

Solutions

• Program no longer tries to continue executing after CALL stack limit failure when “Continue On Error” option is set for a Special Function.
• Non-compiled Special Function programs and subroutines are no longer being called inline from the RLL or from a CALL statement in a compiled Special Function program.
• PID Loops and Alarms correctly write updates to discrete V-Flag addresses.
• Special Function execution now uses memory more efficiently.
• Special Function SCALE and UNSCALE instructions now report an error when the input is out of the range of the engineering units specified.
• Forced bit I/O locations are no longer cleared on a transition to Program.
• When finding an X or Y address in a discrete force, the search will also look for “C” addresses.
• The TEXT instruction decodes properly during the RLL syntax check and no longer causes the Find Opcode function to encounter an error and abandon its search.
• Searching by instruction type now finds all instructions within the same instruction class. (Requires 505 Workshop 4.00 SP1)